This invention relates to high-density electronics packaging. More particularly, the present invention relates to increasing the packing density of integrated circuit chips.
The science of electronics packaging addresses the manner in which one or more integrated circuits, hereinafter xe2x80x9cICs,xe2x80x9d (defined later in this specification) are packaged efficiently and reliably. Packaging-related issues play a significant role in determining the number of ICs that can be placed in an electronics package and the performance of the package.
Electronics packages have a hierarchical structure wherein the smallest devices (i.e., ICs) are incorporated into a larger platform, the larger platform is incorporated into a still larger assemblage, and so forth. This hierarchical structure, which creates packaging efficiencies, is illustrated in FIG. 1, which depicts conventional electronics package 100.
Electronics package 100 consists of a third level electronics package in the form of motherboard 102 that receives a plurality of cards or printed circuit boards (xe2x80x9cPCBxe2x80x9d) 104. Each card 104, which is a second level electronics package, includes a variety of IC chips, which are first level packages. IC chips, such as chip 106, are attached to the card in any of a variety of ways. For example, an IC chip can be attached to substrate 108 forming single-chip module 110 (a first level electronics package) and then attached to card 104, such as by solder bumps 112. Alternatively, an IC chip can be packaged with other IC chips in the form of a multi-chip module 114 (a first level electronics package) and then attached, by pins 116 for example, to card 104. There are many different packaging technologies, as is required, or at least preferred, for handling the variety of semiconductor IC devices (e.g., application-specific ICs, microprocessors, cache memory and main memory) as function, primarily, of IC pin count. See, Lau, Low Cost Flip Chip Technologies for DCA, WLCSP, and PBGA Assemblies, Chapt. 1, (McGraw-Hill, (copyright) 2000).
In electronics packaging, there is a constant drive to improve density. That is, the industry strives for more IC chips per unit volume and more input/output (xe2x80x9cI/Oxe2x80x9d) connections per unit area of circuit board space. In one approach, electronics packaging density is increased at the first packaging level by creating a xe2x80x9cchip-stackxe2x80x9d wherein a plurality of IC chips are directly attached to one another. A high density interconnect scheme typically accompanies the chip-stack, wherein a large number of I/O connections are provided across a relatively small area. The prior art is replete with chip stack packages; a brief survey of such art follows.
U.S. Pat. No. 4,706,166 discloses a horizontal stack of IC chips. All electrical leads of the ICs are on a single access plane that is defined by one side of the stack. Bonding pads are formed on the access plane, and bonding bumps are formed on the bonding pads. Furthermore, strips are formed on the access plane, and bonding bumps are formed on the strips. A substrate has a pattern of metallic conductors that match the pattern on the access plane. The one side of the stack is then attached to a substrate by bonding the bumps that are on the stack to bumps that are disposed on the conductors residing on the substrate.
In U.S. Pat. No. 5,602,420, plural non-packaged semiconductor elements having peripheral bond pads are spacedly stacked in a vertical direction. Corresponding bond pads are soldered with meltable balls to one of a plurality of leads that are perpendicular to the superconductor elements.
U.S. Pat. No. 5,998,864 discloses a vertical stack of bare semiconductor devices. The semiconductor devices are offset in at least one direction so that a portion of each of the semiconductor device is exposed. Conductors attached to the exposed portion of each semiconductor device make electrical contact with a substrate.
U.S. Pat. No. 6,020,629 discloses a package comprising a vertical stack of semiconductor devices. The package includes a plurality of separate substrates each having a semiconductor die mounted thereon. Each substrate has matching patterns of external contacts and contact pads that are formed on opposing sides of the substrate. All die in the package are interconnected through inter-level conductors.
U.S. Pat. No. 6,033,931 discloses a horizontal stack of chips. Electrical connection on each chip is rerouted to one side of the chip, wherein a solder ball is ultimately attached at that point. A three-layer dielectric film consisting, in one embodiment, of polyimide and acrylic, is sandwiched between a major surface of adjacent chips thereby acting as spacers. Each sandwiched dielectric film is recessed relative to the surrounding chips so that the edge side of each chip extends beyond the edge of each dielectric film, forming a castellated profile. Solder balls are attached to the extended side edges, and the solder balls are then attached to a substrate.
In U.S. Pat. No. 6,051,878, a vertical multi-substrate stack is disclosed. The substrates are stacked atop one another using electrically conductive balls or column-like structures. Semiconductor die are connected to one or both sides of each stacked substrate.
U.S. Pat. No. 6,072,233 discloses a vertical stack of fine ball grid array (xe2x80x9cFBGAxe2x80x9d) packages. Each FBGA package includes a substrate that has conductive traces formed on the bottom and top surfaces thereof. The FBGA package further includes an IC that is attached to a die pad that is formed on the top surface of the substrate. The IC has a plurality of bond pads that are disposed over an aperture that is formed in the die pad and the substrate. Wire bonds pass through the aperture and form an electrical connection between the bond pads on the IC and terminal pads on the bottom surface of the substrate. Solder balls that are attached to the conductive traces on the substrate of a first FBGA package are attached to the conductive traces on the substrate of a second FBA package, and so forth, creating a stack of FBGA packages.
U.S. Pat. No. 6,121,676 discloses a vertical stack of ICs. ICs are attached to a flexible substrate, and the substrate is then bent to form a serpentine configuration. In this configuration, the ICs lie one above the other in the form of a vertical stack. Solder balls are used to attach the substrate to the next packaging layer.
In Re. 36,916, a multi-chip memory module includes a plurality of stacked ICs that are disposed between and interconnected by opposing sideboards. The sideboards are circuit boards having a pattern of interconnected vias that receive the pins of the stacked ICs. The pins of the lowermost IC are also attached to a substrate, such as a main circuit board.
U.S. Pat. No. 6,153,929 discloses a vertical stack of ICs. Major surfaces of adjacent ICs are bonded together. Outer leads on opposed side edges of each IC contact flexible conductive buses that terminate in bus ends that are joinable to a PCB.
These stacked-chip packages, and the assembly processes required to fabricate them, are typically quite complex. In fact, new technologies must often be developed to support such designs. As a consequence, the packages are usually high in cost, sometimes of questionable reliability, and are often produced at low yields. The art would benefit, therefore, from a high density electronics package that avoids the drawbacks of the prior art.
The present invention is a high-density electronics package, and a method for making such a package, that avoids much of the complexity of the prior art.
High-density electronics packages described herein compromise a chip-stack that has a plurality ICs that are joined together at opposing major surfaces. A plurality of oblong-shaped xe2x80x9cbumpsxe2x80x9d comprising an electrically-conductive bonding material are disposed in a one-dimensional array along one side of each IC in the chip-slack. The one side of each IC bearing the bumps is aligned with the bump-bearing side of all other ICs in the chip-stack. When so aligned, the one-dimensional array of bumps on each IC collectively defines a two-dimensional array of such bumps.
A portion of each oblong-shaped bump extends beyond the edge of its host IC. This portion of each bump is available to electrically and mechanically connect the chip stack to the next packaging layer (i.e., a second level electronics package), typically a printed circuit board. In fact, some high-density electronics packages in accordance with the illustrative embodiment of the present invention comprise a chip-stack that is attached, in a horizontal disposition, to a second level electronics package. In some of such variations, the second level electronics package has a two dimensional array of I/O pads that are appropriately sized for receiving the exposed array of bumps. After aligning and contacting the bumps of the chip-stack with the I/O pads of the second level package, the bumps are melted and then cooled in a xe2x80x9cre-flowxe2x80x9d process that results in the formation of a bond between each bump and its corresponding I/O pad. The bond mechanically and electrically connects the ICs to the second level package.
A method for forming a high-density electronics package in accordance with the illustrative embodiment of the present invention comprises:
forming oblong-shaped-bumps near an edge of a first side of an IC, wherein a portion of each of the bumps extends beyond a perimeter of the active area of the IC and into the kerf along that side;
removing at least a portion of the kerf along the bump-bearing side, thereby defining a foreshortened side of the IC, wherein a portion of each of the bumps extends beyond an edge of the foreshortened side;
aligning the edge of the foreshortened side of the IC with the edge of a second, similarly prepared IC; and
attaching the ICs at major surfaces thereof such that a portion of each bump extends beyond the edge of the shortened side of each of the ICs and the balance of each bump is sandwiched between the ICs.